Some Considerations About Passive Sharing in Shared-Memory Multiprocessors

نویسندگان

  • Cosimo Antonio Prete
  • Gianpaolo Prina
  • Roberto Giorgi
  • Luigi Ricciardi
چکیده

In a multiprocessor system, process migration guarantees load balance between processors but causes passive sharing, since private data blocks of a process can become resident in multiple caches and generate useless coherence-related overhead. We propose a selective invalidation strategy to eliminate these passive shared copies. The results of trace-driven simulation prove that our strategy can result successful in a number of situations such as the typical case of a general-purpose workstation.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors

ÐIn high-performance general-purpose workstations and servers, the workload can be typically constituted of both sequential and parallel applications. Shared-bus shared-memory multiprocessor can be used to speed-up the execution of such workload. In this environment, the scheduler takes care of the load balancing by allocating a ready process on the first available processor, thus producing pro...

متن کامل

Evaluation of a Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Multithreaded Multiprocessors

Single-chip multiprocessors and multiple-thread architectures are becoming an affordable solution for high-performance general-purpose workstations and servers. On these machines, the workload is typically constituted of both sequential and parallel applications. Shared-bus shared-memory multithreaded multiprocessor can be used to speed-up the execution of such workload. In this environment, th...

متن کامل

An Algorithm for the Classification of Coherence Related Overhead in Shared-Bus Shared-Memory Multiprocessors

This paper describes an algorithm for the classification of coherence overhead in shared-bus shared-memory multiprocessors. This algorithm is applicable to Write Update, Write Invalidate and Hybrid protocols and models the effect of finite size (real) cache. It differs from previous classifications because it classifies any sources of coherence overhead, i.e. invalidation miss, invalidate and w...

متن کامل

Simulation study of memory performance of SMP multiprocessors running a TPC-W workload

The infrastructure to support electronic commerce is one of the areas where more processing power is needed. A multiprocessor system can offer advantages for running electronic commerce applications. The memory performance of an electronic commerce server, i.e. a system running electronic commerce applications, is evaluated in the case of shared-bus multiprocessor architecture. The software arc...

متن کامل

False Sharing and Spatial Locality in Multiprocessor Caches

The performance of the data cache in shared-memory multiprocessors has been shown to be diierent from that in uniprocessors. In particular, cache miss rates in multiprocessors do not show the sharp drop typical of uniprocessors when the size of the cache block increases. The resulting high cache miss rate is a cause of concern, since it can signiicantly limit the performance of multiprocessors....

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1997